`include "PRV564Config.v"
`include "PRV564Define.v"
module VFIB_simtop(

);
    reg                     CLK, ARST;
//-----------------FIB Access queue signals---------------------
    reg                     VFIBSi_REQ;         //Request for using bus
    wire             		VFIBSo_ACK;         //ack for valid (read a new access from FIFO)
    wire                    VFIBSo_FULL;
    reg             		VFIBSi_WREN;        //Write to FIFO enable
    reg [7:0]       		VFIBSi_ID;
    reg [7:0]       		VFIBSi_CMD;
    reg [3:0]       		VFIBSi_BURST;
    reg [3:0]       		VFIBSi_SIZE;
    reg [`XLEN-1:0] 		VFIBSi_ADDR;      
    reg [`XLEN-1:0] 		VFIBSi_DATA;
//----------------FIB reply signals------------------------------
    wire [7:0]       		VFIBSo_ID;
    wire [7:0]       		VFIBSo_RPL;			//应答
    wire             		VFIBSo_V;
//  wire             		FIBo_ADDR,
    wire [`XLEN-1:0] 		VFIBSo_DATA;
//----------------SRAM port----------------------------------------
    wire                     SRAM_WREN;
    wire [7:0]               SRAM_BSEL;
    wire [`XLEN-1:0]         SRAM_ADDR;
    wire [`XLEN-1:0]         SRAM_DATAi;
    wire [`XLEN-1:0]         SRAM_DATAo;
initial begin
    CLK          = 1'b0;
    ARST         = 1'b1;
    VFIBSi_WREN  = 1'b0;        //Write to FIFO enable
    VFIBSi_ID    = 8'b0;
    VFIBSi_CMD   = `FIB_CMD_NOOP;
    VFIBSi_BURST = 4'h0;
    VFIBSi_SIZE  = 4'h4;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h11451419;
#100
    ARST         = 1'b0;
#100
wait(!VFIBSo_FULL)begin         //数据帧1: Sig write
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h2;
    VFIBSi_CMD   = `FIB_CMD_SIGW;
    VFIBSi_BURST = 4'h0;
    VFIBSi_SIZE  = 4'h4;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h11451419;
end
#10
wait(!VFIBSo_FULL)begin         //数据帧2 ： Sig read
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h3;
    VFIBSi_CMD   = `FIB_CMD_SIGR;
    VFIBSi_BURST = 4'h0;
    VFIBSi_SIZE  = 4'h4;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'hx;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h0;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h1;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h2;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h3;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h4;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h5;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQW;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h6;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h4;
    VFIBSi_CMD   = `FIB_CMD_SEQE;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'h7;
end
#10
wait(!VFIBSo_FULL)begin
    VFIBSi_WREN  = 1'b1;
    VFIBSi_ID    = 8'h5;
    VFIBSi_CMD   = `FIB_CMD_SEQR;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'hx;
end
#10
    VFIBSi_WREN  = 1'b0;
    VFIBSi_ID    = 8'hx;
    VFIBSi_CMD   = `FIB_CMD_SEQR;
    VFIBSi_BURST = 4'h3;
    VFIBSi_SIZE  = 4'h8;
    VFIBSi_ADDR  = 64'h0;
    VFIBSi_DATA  = 64'hx;
end

always begin
    #5 CLK = ~CLK;
end

Virtual_FIB_Slave                   DUT(
    .CLKi                   (CLK),
    .RSTi                   (ARST),
//--------------------FIB interface----------------
    .VFIBSi_REQ             (VFIBSi_REQ),         //Request for using bus
    .VFIBSo_ACK             (VFIBSo_ACK),         //ack for valid (read a new access from FIFO)
    .VFIBSo_FULL            (VFIBSo_FULL),
    .VFIBSi_WREN            (VFIBSi_WREN),        //Write to FIFO enable
    .VFIBSi_ID              (VFIBSi_ID),
    .VFIBSi_CMD             (VFIBSi_CMD),
    .VFIBSi_BURST           (VFIBSi_BURST),
    .VFIBSi_SIZE            (VFIBSi_SIZE),
    .VFIBSi_ADDR            (VFIBSi_ADDR),
    .VFIBSi_DATA            (VFIBSi_DATA),
    //            reply to master
    .VFIBSo_ID              (VFIBSo_ID),
    .VFIBSo_RPL             (VFIBSo_RPL),			//应答
    .VFIBSo_V               (VFIBSo_V),
//  .FIBo_ADDR,
    .VFIBSo_DATA            (VFIBSo_DATA),
//----------------SRAM interface-----------------------
// 注意！这个SRAM是异步读出的，因此仅适用于仿真
    .SRAM_WREN              (SRAM_WREN),
    .SRAM_BSEL              (SRAM_BSEL),
    .SRAM_ADDR              (SRAM_ADDR),
    .SRAM_DATAi             (SRAM_DATAi),
    .SRAM_DATAo             (SRAM_DATAo)

);

simRAM          simRAM(
    .SRAM_CLKi              (CLK),
    .SRAM_WREN              (SRAM_WREN),
    .SRAM_BSEL              (SRAM_BSEL),
    .SRAM_ADDR              (SRAM_ADDR),
    .SRAM_DATAi             (SRAM_DATAi),
    .SRAM_DATAo             (SRAM_DATAo)
);

always@(posedge CLK)begin
    if(VFIBSo_V)begin
        $display("Valid reply, ID=%h, RPL=%h, DATA=%h", VFIBSo_ID, VFIBSo_RPL, VFIBSo_DATA);
    end
end

endmodule